Reducing power consumption during data transfers in the interconnects of integrated circuits (ICs) is important in the development of IC design. Certain methods have been developed to efficiently transfer data, including source synchronous interfaces. Source synchronous interfaces are often used in high-speed data transfer applications, such as double data rate (DDR) synchronous DRAM systems. Source synchronous clocking refers to the technique of sourcing a clock along with data on the same line. The timing of unidirectional data signals is referenced to a clock sourced by the same device that generates those signals, and not to an external or global clock that is generated by a bus master. Source synchronous bus transmission protocol uses clock, and data-valid signals to mark in time when the transmitted data is valid. In general, the switching power in a circuit is directly proportional to the bus throughput (frequency of the bus) and the physical length of the bus. As the lengths between repeaters in source synchronous bus systems are longer than the regular synchronous buses, the source synchronous bus is a better power-solution for long bus connections. It is thus especially important to reduce power in these systems.
FIG. 1A illustrates a typical source synchronous bus interface transmitting data between and transmitter 101 and receiver 103, as presently known. The clock is sourced from the same device as the data, and latches the data on either a clock edge or shifted clock edge. FIG. 1B illustrates the timing of a source synchronous bus at the transmitter 101, as known in prior art systems. The timing diagram of FIG. 1B shows the timing relationships between a periodic clock signal 102, data 106, and the data valid signal (valid) 104. The data 106 is valid only during the clock periods during which the data valid signal 104 is active. In present source synchronous bus systems, the clock signal 102 is sent until the data reaches the receiver stage. It should be noted that the data line shown in FIG. 1A represents any number of signals and wires depending on the size of the data bus.
One issue associated with source synchronous circuits is that the transitions of the clock and valid signals contribute to overall power consumption in the IC. Source synchronous bus circuits send data, data-valid, and clock signals together from a transmitter through a number of repeaters to a receiver. The toggling clock and data valid signals draw power, which can become excessive under certain operational conditions. To overcome issues, such as power consumption, certain known systems manage the clock signal. For example, clock gating may be used in source-destination synchronous bus protocols. In source synchronous bus systems with clock gating, as the repeaters invert the clock signal, they require the clock to be driven by the transmitter until the data arrives at the destination.
Another issue with source synchronous circuits is the potential of generating electrical noise, which may cause timing instability. Source synchronous bus systems rely on clock signal availability as the data is transmitted so that the data and clock signals are sent together. However, variability along the transmission lines requires the clock to have a register refresh as it travels along the bus. In present systems, the clock toggles continuously and each transition requires a recharge of the entire length of the clock line such that the change is propagated through the entire bus. The recharge of the bus costs power, and also generates some amount of electrical noise, which may leak into timing of signals. This noise leakage may in turn cause synchronization problems.
What is needed therefore, is a system that minimizes signal transitions in a source synchronous bus system to reduce power consumption, minimize noise generation and improve timing synchronicity.
The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches.